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Static timing analysis
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#	Item
51	Understanding Timing in Altera CPLDs AN[removed] Add to Reading List Source URL: www.altera.com Language: English - Date: 2010-11-29 20:41:01 Altera Quartus Flip-flop Altera Static timing analysis Complex programmable logic device Electronic engineering Electronics Digital electronics
52	Application Note AC198 Clock Skew and Short Paths Timing Add to Reading List Source URL: www.actel.com Language: English - Date: 2012-11-27 04:53:29 Electromagnetism Computer memory Clock skew Digital electronics Formal methods Flip-flop Clock distribution network Static timing analysis Counter Electronic engineering Electronics Clock signal
53	684 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 6, JUNE 2007 Add to Reading List Source URL: www.cs.unc.edu Language: English - Date: 2007-08-30 12:00:36 Electronics Logic gates Formal methods Computer memory Flip-flop Pipeline Asynchronous system C-element Static timing analysis Electronic engineering Computer architecture Digital electronics
54	PDF Document Add to Reading List Source URL: moss.csc.ncsu.edu Language: English - Date: 2007-03-19 10:17:37 Electronics Technology Programming language implementation Central processing unit Static timing analysis CPU cache Embedded system Assembly language Profiling Real-time computing Worst-case execution time Computing
55	Microsoft Word - CummingsSNUG2001SJ_AsyncClk_rev1_2.doc Add to Reading List Source URL: www.sunburst-design.com Language: English - Date: 2005-06-20 14:45:28 Formal methods Digital electronics Hardware description languages Clock signal Electrical circuits Flip-flop Static timing analysis Clock Synchronization Electronic engineering Electronics Electromagnetism
56	PDF Document Add to Reading List Source URL: www.nileshgoel.com Language: English - Date: 2011-09-14 04:00:01 Flip-flop Contamination delay Sequential logic Static timing analysis Propagation delay Clock signal Signal edge Scan chain Verilog Electronic engineering Digital electronics Electronics
57	PDF Document Add to Reading List Source URL: www.eda.org Language: English - Date: 1997-07-30 16:59:35 Digital electronics Hardware description language Static timing analysis Verilog Electronic engineering Electronic design automation Standard Delay Format
58	PDF Document Add to Reading List Source URL: w2.cadence.com Language: English - Date: 2004-01-07 14:00:56 Electronic design Signal integrity Design closure Static timing analysis Standard cell Delay calculation Integrated circuit design Signoff Electronic engineering Electronic design automation Electronics